کد مدار
;LIBRARY ieee
;USE ieee.std_logic_1164.ALL
;USE ieee.std_logic_unsigned.ALL
---------------------------------------------
ENTITY Example IS
; PORT ( x,y,B : IN std_logic
;D,E : OUT std_logic)
;END Example
---------------------------------------------
ARCHITECTURE behave OF Example IS
;signal in1,in2,in3,in4,in5: std_logic
BEGIN
process
;variable temp:std_logic
begin
;in1<=x xor y
;in2<= not x
;in3<= not in1
;in4<= in2 and y
;in5<= in3 and B
;temp:= x nor B
; D <= not temp
; E<= in5 or in4
;end process
;End behave